The monolithic integration of gallium arsenide (GaAs) photonic and electronic materials and devices with host substrates, such as silicon (Si), glass, and polymers, will enable the fabrication of the next generation of integrated circuits, particularly, integrated circuit "cubes" having a massive three dimensional communication network and optoelectronic integrated circuits. A standard technique for GaAs on Si integration is heteroepitaxial growth, which is described in H. Choi J. Mattia, G. Turner, and B. Y. Tsauer, "Monolithic Integration of GaAs/AlGaAs LED and Si Driver Circuit", IEEE Electron Dev. Lett., vol.9, pp. 512-514, 1988, incorporated herein by reference. However, the crystal quality of this heteroepitaxial material is often inadequate for many optical applications.
An integration method which seeks to preserve the high material quality of lattice-matched growth is the epitaxial lift-off process developed by Bell Communications Research, Inc., (Bellcore), as described in E. Yablonovitch, T. J. Gmitter, J. P. Harbison, and R. Bhat, "Double Heterostructure GaAs/AlGaAs Thin Film Diode Lasers on Glass Substrates", IEEE Phot. Tech. Lett., 1, pp. 41-42, 1989, incorporated herein by reference. Essentially, a thin aluminum arsenide (AlAs) sacrificial layer is grown on a GaAs substrate, and then GaAs/AlGaAs device epitaxial layers are grown on top of the AlAs layer. The GaAs/AlGaAs lattice-matched epitaxial layers are separated from the growth substrate by selectively etching the AlAs sacrificial layer. These device layers are then mounted in a hybrid fashion onto a variety of host substrates. The device layers are of high quality and are currently being used for the integration of GaAs/AlGaAs materials onto host substrates, such as Si, glass, lithium niobate, and polymers.
However, although the Bellcore technique yields high quality material, it has several problems, including the inability to align and selectively deposit the devices. Moreover, there are difficulties in contacting both sides of the devices. Hence, at present, the Bellcore technique is inadequate for producing emitters and receivers for three dimensional integrated circuits, described in detail hereafter.
For an n.times.n array processor, the number of input/output (I/O) connections required for optimum performance is on the order of n.sup.2. However, the number of connections available in a conventional two dimensional integrated circuit is typically on the order of 4.times.D, as a result of space limitations thereby creating a connection bottleneck. Moreover, as the number of processing elements increases, connection availability becomes even more limited. Thus, the connection bottleneck substantially limits the processing density and speed of array processors implemented with integrated circuit technology.
The connection bottleneck can be overcome through the use of three dimensional communication at the I/O interface and within the integrated circuit itself. I/O connections can be implemented around the entire outside of the integrated circuit, including the top and bottom as well as the sides. Furthermore, intercommunication between integrated circuit layers as well as intracommunication within the circuit layers are essential. In other words, integrated circuits can be converted from a two dimensional plane-like structure into a three dimensional cube-like structure. The implementation of three dimensional communication would enable massive parallel data transfer and signal processing at all processing points in an array, thereby increasing the throughput and speed of system computation through elimination of the connection bottleneck.
The applications for three dimensional communication are numerous. For example, neural networks and, specifically, learning neural networks, would particularly benefit because of their array structure. See, for example, C. A. Mead, Analog VLSI and Neural Systems, Addison-Wesley, 1989, which is incorporated herein by reference, and which discloses the benefit of three dimensional communication to neural networks.
As another example, consider the benefit to an optical imaging array which converts light from an image into an electronic manifestation. The optical imaging array could be disposed on an outer plane of a three dimensional integrated circuit cube. The optical imaging array would benefit from three dimensional connection because each optical detector could then be connected directly to corresponding signal processing circuitry. As a result, (1) image arrays could be larger in area and in number of detectors; (2) extremely high throughput could be provided due to massive parallel processing; and (3) the ultimate number of array outputs could be reduced because of the pre-processing of each pixel data by corresponding processing circuitry.
In the art, three dimensional integration of circuitry has only begun to evolve. The preliminary research involving this type of integration is discussed hereafter.
A thermomigrated feedthrough technique is currently under development, but very little has been published in open literature about this technique. However, the thermomigrated feedthrough technique involves thermomigrating aluminum signal paths, or "feedthroughs," into a wafer to provide communication between the front and back side of a silicon (Si) wafer. Because the aluminum is a p-type dopant and the surrounding Si wafer is an n-type dopant, a pn junction is created at the signal path interfaces. The pn junction isolates the thermomigrated feedthroughs from each other and thus prevents cross-talk. Furthermore, microbridge connections are used to connect separate wafers together. For more information on microbridge connections, see J. Little, R. Etchells, J. Grinberg, S. Laub, J. Nash, and M. Yung, International Conference on Wafer Scale Integration Proceedings, pp. 55-92, 1989, the disclosure of which is incorporated herein by reference.
Although the thermomigrated feedthrough technique has advantages, it remains problematic. First, most fabrication processes for complimentary metal oxide semiconductor (CMOS) devices use a p-type Si substrate wafer. The thermomigrated feedthrough technique can only use n-type wafers. Second, the pn junction isolation creates a large substrate capacitance for each feedthrough. This predicament capacitively loads the circuitry connected to the feedthroughs, thereby decreasing signal speed or requiring specialized high powered drive circuitry. In addition, the area occupied by the feedthrough I/O interconnect may be physically large because a small aluminum dot on the wafer surface will spread in area as well as in depth. Finally, the cost of the thermomigrated feedthrough technique may make it prohibitive for inexpensive integration.
Another three dimensional integration technique involves growing Si layers on top of insulating layers which have been deposited onto a Si wafer already having circuitry. Thus far, the research has focused on the recrystallization of the deposited Si, because the deposited Si tends to grow in amorphous form on the Si wafer. However, the heat generated in this growth and recrystallization technique, which often utilizes a laser to perform the recrystallization, is usually detrimental to the existing circuitry on the Si wafer situated below.
A flip chip technique for three dimensional integration involves the bonding of two wafers. This technique is described in IEEE Transcript On Electronic Devices, Volume 38, No. 5, Special Issue On Solid-State Image Sensors, 1991, which is incorporated herein by reference. This technique is undesirably limited to the connection of two layers of devices. In addition, flip chip bonding also suffers from yield and reliability problems.
Still another technique for three dimensional integration involves growing a photoconversion layer on top of Si circuitry. This technique is fully described by S. Manabe and Y. Mastunaga, IEEE Transcript On Electronic Devices, Volume 38, No. 8, pp. 1765-1771, 1991, the disclosure of which is incorporated herein by reference. The photoconversion layer integration technique is also an integration scheme which is limited to the connection of only two layers of devices. Furthermore, the photoconversion layer integration technique is extremely limited in device scope because only amorphous Si photoconversion layers can be used for the technique.
Yet another three dimensional integration technique involves multi-chip module technology. In this technique, individual chips are placed onto a highly interconnected substrate in a hybrid fashion to form a "multi-chip module." Complex interconnections between the chips are achieved by photolithographically-defined interconnects in the prefabricated substrate. At present, these multi-chip modules are finding some commercial application in computational systems such as computers. However, for computational systems having a very large number of processors, such as array processors, the technology is limited by the finite number of interconnections which can be achieved by the substrate.
Finally, three dimensional integration using optical interconnects has been proposed, but demonstrated only to a very limited extent in the art. For example, discrete light emitters and detectors, together with associated circuitry, have been crudely mounted on an insulating substrate, as described in R. K Kostuk, J. W. Goodman, and L. Hesselink, "Optical Imaging Applied to Microelectronic Chip-to-Chip Interconnections," Appl. Opt., Vol. 24, p. 2851, 1985, incorporated herein by reference. Light emitters and detectors have also been formed on Si substrates, as discussed in M. J. Goodwin, A. J. Moseley, D. J. Robbins, M. Q. Kearley, J. Thompson, D. Clewitt, R. C. Goodfellow, and I. Bennion, "Hybridised Optoelectronic Modulator Arrays for Chip-to-Chip Optical Interconnection," SPIE Proc., Vol. 1281, p. 207, 1990; A. Yariv, "The Beginning of Integrated Optoelectronic Circuits," IEEE Trans. Electron Devices, Vol. ED-31, p. 1656, 1984; and P. J. Ayliffe, J. W. Parker, and A. Robinson, "Comparison of Optical and Electrical Interconnections at the Board and Backplane Levels,.infin. SPIE Proc., Vol. 1281, p.2, 1990, the disclosures of which are incorporated herein by reference.
A more notable attempt for optical integration was recently described in "Through-Wafer Optical Communication Using Monolithic InGaAs-on-Si LED's and Monolithic PtSi-Si Schottky-Barrier Detectors", G. W. Turner, C. K. Chen, B. Y. Tsaur, and A. M. Waxman, IEEE Photonics Technology Letters, Vol. 3, No. 8, August 1991, the disclosure of which is incorporated herein by reference. This technique involves communication through Si wafers by using a light emitter fabricated on one Si wafer and a detector fabricated on a second Si wafer. The emitter and detector are arranged in a stack configuration. The emitter is a doubleheterostructure InGaAs-InAlAs LED fabricated on a p-type Si substrate, and the detector is a PtSi Schottky-barrier diode fabricated on an n-type Si substrate.
Although the foregoing optical integration technique shows much promise in the area of three dimensional integration, it has severe limitations. Two Si wafers of different dopant type must be utilized. Moreover, growth of the emitter and detector on the Si wafers can cause damage to surrounding circuitry and/or limit the ability to fabricate certain circuitry within the proximity of the emitter and detector.
In essence, all optical integration techniques in the conventional art fall short of teaching a method for fabricating a fully operative and expansive three dimensional communication network within an integrated circuit.